TBU Publications
Repository of TBU Publications

Distortion caused by controlling transistor implemented in the voltage controlled amplifier

DSpace Repository

Show simple item record

dc.title Distortion caused by controlling transistor implemented in the voltage controlled amplifier en
dc.contributor.author Pospíšilík, Martin
dc.contributor.author Navrátil, Milan
dc.contributor.author Adámek, Milan
dc.relation.ispartof 13th International Conference ELEKTRO 2020, ELEKTRO 2020 - Proceedings
dc.identifier.isbn 978-1-72817-542-3
dc.date.issued 2020
utb.relation.volume 2020-May
dc.event.title 13th International Conference ELEKTRO, ELEKTRO 2020
dc.event.location online
dc.event.sdate 2020-05-25
dc.event.edate 2020-05-28
dc.type conferenceObject
dc.language.iso en
dc.publisher Institute of Electrical and Electronics Engineers Inc.
dc.identifier.doi 10.1109/ELEKTRO49696.2020.9130305
dc.relation.uri https://ieeexplore.ieee.org/document/9130305
dc.subject distortion en
dc.subject harmonics en
dc.subject linearization en
dc.subject voltage controlled amplifier en
dc.description.abstract This paper describes a voltage controlled amplifier with linearized response to the controlling voltage and discusses its harmonic distortion. As a controlling element, a JFET transistor has been utilized. The design of the amplifier has been made with the aid of Maple mathematical software and National Instruments Multisim circuit simulator. During the simulations, it was found that the controlling transistor would probably introduce significant distortion into the signal path. Therefore a set of measurements on real circuit was made in order to verify that the SPICE model of the transistor provided relevant results during the simulation. Both, the simulated and the really measured parameters of the amplifier are discussed within the framework of this paper. ©2020 IEEE en
utb.faculty Faculty of Applied Informatics
dc.identifier.uri http://hdl.handle.net/10563/1010310
utb.identifier.obdid 43882140
utb.identifier.scopus 2-s2.0-85104474723
utb.source d-scopus
dc.date.accessioned 2021-05-14T12:05:19Z
dc.date.available 2021-05-14T12:05:19Z
dc.description.sponsorship Ministerstvo Školství, Mládeže a Tělovýchovy, MŠMT: LO1303, MSMT-7778/2014
utb.ou CEBIA-Tech
utb.contributor.internalauthor Pospíšilík, Martin
utb.contributor.internalauthor Navrátil, Milan
utb.contributor.internalauthor Adámek, Milan
utb.fulltext.sponsorship This paper is supported by the Ministry of Education, Youth and Sports of the Czech Republic within the National Sustainability Programme project No. LO1303 (MSMT-7778/2014).
utb.scopus.affiliation Faculty of Applied informatics, Tomas Bata University in Zlin, Zlin, Czech Republic
utb.fulltext.projects LO1303
utb.fulltext.projects MSMT-7778/2014
Find Full text

Files in this item

Show simple item record